wiki:camera_fpga_registers

Version 4 (modified by Uros Stevanovic, 13 years ago) (diff)

adding LED description

Registers

Address Short Name Mode Size Description
0x0000 - 0x8FFF DMA Registers
0x9000 spi_conf_in RW 32 CMOSIS control register
0x9008 spi_conf_out R 32 CMOSIS status register
0x9100 - 0x910F DMA Test Application Registers


spi_conf_in

bits Mode Description
0..7 RW data
8..14 RW address
15 RW Read(0)/Write(1)


spi_conf_out

bits Mode Description
0..7 R data
8..14 R address
15 R Read(0)/Write(1)
16 R ?
17 R ready bit
18 R error bit


LED description

LED name Connection Description
DS11 ~trn_lnk_up_n PCIe link is ON
DS9 led_ctr Flash if core_clk_i_div2 is ON
DS10 lane_width_error ON if OK, else flashes
DS15 ctrl_wd_lock ON if OK
DS14 data_wd_lock_AND ON if OK
DS22 MIG clk flash if OK
DS21 phy_init_done DDR init OK
DS16 c2s1_dst_rdy DMA ready to receive data
DS17 c2s1_src_rdy Logic is ready to send data
DS19 dma_rst1 Reset
DS18 FSM_Master_Ctrl_no_activity_o if ON, no data from CMOSIS
DS20 enough_RAM_space FIFO 64_255 is almost full, stop the Data Taking


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