Registers

• Registers of DMA Engine

Address	Short Name	Mode	Size	Description
0x0000 - 0x8FFF				DMA Registers
0x9000	spi_conf_in	RW	32	CMOSIS control register
0x9008	spi_conf_out	R	32	CMOSIS status register
0x9100 - 0x910F				DMA Test Application Registers

spi_conf_in

bits	Mode	Description
0..7	RW	data
8..14	RW	address
15	RW	Read(0)/Write(1)

spi_conf_out

bits	Mode	Description
0..7	R	data
8..14	R	address
15	R	Read(0)/Write(1)
16	R	?
17	R	ready bit
18	R	error bit

LED description

LED name	Connection	Description
DS11	~trn_lnk_up_n	PCIe link is ON
DS9	led_ctr	Flash if core_clk_i_div2 is ON
DS10	lane_width_error	ON if OK, else flashes
DS15	ctrl_wd_lock	ON if OK
DS14	data_wd_lock_AND	ON if OK
DS22	MIG clk	flash if OK
DS21	phy_init_done	DDR init OK
DS16	c2s1_dst_rdy	DMA ready to receive data
DS17	c2s1_src_rdy	Logic is ready to send data
DS19	dma_rst1	Reset
DS18	FSM_Master_Ctrl_no_activity_o	if ON, no data from CMOSIS
DS20	enough_RAM_space	FIFO 64_255 is almost full, stop the Data Taking

Frame rate

Frame rate in streaming mode: Total_readout_time + delay_between_frames
register_73 = 10, by default
number_of_outputs = 16/pow(2,output_mode)
master_clk_period = (bit_mode) ? 1/48MHz : 1/40MHz
Total readout time:Exposure time + FOT (frame overhead time) + image readout time
FOT = (register_73 + (2* 16/number_of_outputs)) * 129 * master_clk_period, where register_73 has default value of 10
image_readout_time = (129 * master_clk_period * 16/number_of_outputs) * number_of_lines
delay_between_frames = trigger_period * 8ns