Changes between Version 3 and Version 4 of camera_fpga_registers


Ignore:
Timestamp:
Oct 27, 2011, 2:50:25 PM (13 years ago)
Author:
Uros Stevanovic
Comment:

adding LED description

Legend:

Unmodified
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  • camera_fpga_registers

    v3 v4  
    2828
    2929[[BR]]
     30
     31= LED description =
     32||= LED name =||= Connection =||= Description =||
     33|| DS11 || ~trn_lnk_up_n || PCIe link is ON ||
     34|| DS9 || led_ctr || Flash if core_clk_i_div2 is ON ||
     35|| DS10 || lane_width_error || ON if OK, else flashes ||
     36|| DS15 || ctrl_wd_lock || ON if OK ||
     37|| DS14 || data_wd_lock_AND || ON if OK ||
     38|| DS22 || MIG clk || flash if OK ||
     39|| DS21 || phy_init_done || DDR init OK ||
     40|| DS16 || c2s1_dst_rdy || DMA ready to receive data ||
     41|| DS17 || c2s1_src_rdy || Logic is ready to send data ||
     42|| DS19 || dma_rst1 || Reset ||
     43|| DS18 || FSM_Master_Ctrl_no_activity_o || if ON, no data from CMOSIS ||
     44|| DS20 || enough_RAM_space || FIFO 64_255 is almost full, stop the Data Taking ||
     45
     46[[BR]]