Northwest Logic Delivery for KIT_PN2002_V6_x8_Gen2 (Version 1.00) Date: 11/26/2013 10:18
========================================================================================

Delivery Notes
--------------

Included:

  Northwest Logic DMA Back-End Core
  Northwest Logic Expresso Reference Design
  Northwest Logic PCIe Bus Functional Model
  Northwest Logic PCIe Core Model
  Northwest Logic Expresso Testbench

Xilinx Hard PCIe Core
---------------------
This release uses the Xilinx Hard PCIe Core.

To generate the Xilinx PCIe core files, open a command window in
the ./pcie directory and type:

vivado -mode batch -source build_pcie.tcl


Reference Design
----------------
A full reference design has been provided which implements the following
resources:
  BAR0   - Registers
  BAR1/2 - Map to the same internal SRAM resource

The reference design provides a highly useful starting point for customer
designs as it implements register and target resources which are common
to most designs.

A full simulation and route of the reference design has been provided to
get customers up and going quickly.


Setting up Xilinx Models for Simulation
--------------------------------------------------------
Xilinx uses SecureIP libraries for the simulation models of the PHY used in
the fpga.

Prior to running the provided reference design simulation, it is necessary
to use the Xilinx Simulation Library Compilation Wizard to compile the
Xilinx SecureIP libraries and to configure your simulator.


Simulation
---------------------
A ModelSim simulation script has been included which you can use to
simulate the reference design. You can modify the ref_design_ts.v file
to change the stimulus of the simulation. To run the simulation:
open ModelSim, change to the tb directory and type:

> do sim.do



Route
-----

An ISE build script is included to build the reference design for the Xilinx
ML605 development board with an XC6V240T FPGA using a 250 MHz reference clock.

The build_opts.f file can be modified to change the place-and-route command
line parameters for the build.

To build the FPGA, run the following batch file from the ./route directory
on the command-line:

> build_fpga_ise.pl -f build_opts.f


Docs
----
User Guides are available in the doc directory



Support
-------
I look forward to supporting you in your use of the provided cores.
Please contact me at:

    Mark Wagner
    Senior Design Engineer
    Northwest Logic
    1100 NW Compton Drive, Suite 100
    Beaverton, OR 97006
    Email: mwagner@nwlogic.com
    Phone: 503.533.5800 x307



File Descriptions
-----------------

  Xilinx Virtex-6 Hard PCIe Core:
     - coregen\v6_pcie_v2_5.xco (top-level)
     - coregen\coregen.cgp

  Northwest Logic DMA Back-End:
    simulation model:
     - models\dma_back_end_pkt.vp (top-level)
    route netlist:
     - netlist\dma_back_end_pkt_enc.v

  Northwest Logic Expresso Reference Design:
     - rtl_ref_design\ref_inferred_block_ram.v
     - rtl_ref_design\register_example.v
     - rtl_ref_design\target_example.v
     - rtl_ref_design\c2s_pkt_streaming_fifo.v
     - rtl_ref_design\c2s_adr_pkt.v
     - rtl_ref_design\packet_check.v
     - rtl_ref_design\packet_gen.v
     - rtl_ref_design\ref_tiny_fifo.v
     - rtl_ref_design\s2c_pkt_streaming_fifo.v
     - rtl_ref_design\s2c_adr_pkt.v
     - rtl_ref_design\ref_sc_fifo_shallow_ram.v
     - rtl_ref_design\ref_dc_fifo_shallow_ram.v
     - rtl_ref_design\ref_dc_fifo.v
     - rtl_ref_design\ref_inferred_shallow_ram.v
     - rtl_ref_design\ref_dc_fifo_adv_block_ram.v
     - rtl_ref_design\ref_gray_sync_bus.v
     - rtl_ref_design\ref_bin_to_gray.v
     - rtl_ref_design\ref_gray_to_bin.v
     - rtl_ref_design\sdram_dma_ref_design_pkt.v
     - rtl_ref_design\dma_ref_design_pkt.v
     - rtl_ref_design\xil_pcie_wrapper.v
     - rtl_ref_design\sram_mp.v

  Northwest Logic PCIe Bus Functional Model:
     - models\pcie_bfm_x8.v

  Northwest Logic PCIe Core Model:
     - models\bfm_pcie_core_vc1.vp (top-level)

  Northwest Logic Expresso Testbench:
     - tb\report_assertions.v
     - tb\ref_design_ts.v
     - tb\tb_top.v (top-level)
     - tb\direct_dma_bfm.v
     - tb\glbl.v
     - tb\master_bfm.v

